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1 ? fn7445.0 isl97522 4-channel tft-lcd supply the isl97522 represents a 4-channel supply control ic for use in large panel tft-lcd displays. supporting inputs from 4.5v to 13v, the isl97522 incl udes a boost controller to achieve the required a vdd output voltage. both v on and v off are generated using off-chip charge-pumps which are then post regulated using on-board ldo controllers. the logic supply is generated using an internal non- synchronous buck controller. this controller runs at 180 out of phase with the a vdd supply to minimize input noise. the a vdd , v off , and v on outputs are automatically sequenced as a vdd , v off , and v on . by using an optional external series transistor with a vdd (q1), the start-up sequence can be adjusted to voff, a vdd and then v on . a v on slicing circuit is also included to reduce lcd flicker. the isl97522 also incorporates a fault protection circuit that can disable the ic and turn off all outputs when an output short is detected. (note that to protect a vdd a single external transistor is required). features ? 4.5v to 13v input ? boost controller for a vdd ? regulated ldos for v off and v on ? buck controller for logic output ?v on slicing circuit ? fully fault-protected ? programmable sequence ? 1mhz switching frequency ? 38 ld qfn package ? pb-free plus anneal available (rohs compliant) applications ? lcd-tvs (up to 50?+) ? lcd monitors (15?+) ? industrial/medical lcd displays pinout isl97522 (38 ld qfn) top view ordering information part number (note) part marking tape & reel package (pb-free) pkg. dwg. # ISL97522IRZ-TK isl 97522irz 13? (1k pcs) 38 ld qfn l38.5x7b isl97522irz-t isl 97522irz 13? (4k pcs) 38 ld qfn l38.5x7b note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. thermal pad 31 30 29 28 27 26 25 38 37 36 35 34 13 14 15 16 17 1 2 3 4 5 6 7 drvn delb fbn vcc1 fbb isadjb iladjb fbp vref acgnd nc drvp nc vdcp src com drn enl ctl isinb vin en vhil lx 8 9 24 23 18 33 19 32 vdc isadjl drvl pgndp cintb drvb cdly vcc2 10 pgndb 11 vhib 12 nc 22 cintl 21 iladjl 20 pbl data sheet december 13, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn7445.0 december 13, 2006 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = +25c) thermal information maximum pin voltages, all pins except below . . . . . . . . . . . . . . 6.5 v vin , en ,enl, lx,vhil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25v vdelb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36v vdrvp, vsinb, src, com, drn . . . . . . . . . . . . . . . . . . . . . . .36v vdrvn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20v operating conditions input voltage range, v in . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 13v boost output voltage range, a vdd . . . . . . . . . . . . . . +15v to +25v v on output range, v on . . . . . . . . . . . . . . . . . . . . . . . +15v to +32v v off output range, v on . . . . . . . . . . . . . . . . . . . . . . . . -15v to -5v input capacitance, c in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2x10f boost inductor, l1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3h to 10h output capacitance, c out . . . . . . . . . . . . . . . . . . . . . . . . . . 4x10f buck inductor, l2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3h to 10h operating ambient temperature range . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . .-40c to +125c thermal resistance ja (c/w) jc (c/w) 38 ld qfn package (notes 1, 2). . . . . 33 4.5 caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = 5v, a vdd = 15v, v on = 20v, v off = -9v, v logic = 3v, over temperature from -40c to +85c parameter description condition min typ max unit general v in input voltage 4.5 13.2 v i s sum quiescent current into vin en = 0, enl = 0 3 ma en = enl = 1, switching 15 ma f osc oscillator frequency 850 1000 1100 khz v ref reference voltage t a = +25c 1.192 1.215 1.235 v 1.190 1.215 1.237 v a vdd v fbb feedback reference voltage t a = +25c 1.195 1.208 1.221 v 1.193 1.208 1.223 v v f_fbb fbb fault trip point v fbb falling 0.85 0.9 0.95 v d min minimum duty cycle 19 25 % d max maximum duty cycle 80 86 % eff boost efficiency 90 % i fbb fbb input bias current 25 na r lineb line regulation c int = 2.2nf, v in = 4.5v to12v, i o =100ma 0.01 0.25 %/v r loadb load regulation c int = 2.2nf, v in = 5v, i avdd = 100ma to 350ma 0.03 0.25 % r onb gate drive on resistance pull-up 3.6 pull-down 1.9 isl97522
3 fn7445.0 december 13, 2006 i peakb peak drive current source 600 ma sink 900 ma i isadjb i sadjb output current r sadjb = 30k 10 15 25 a i iladjb i ladjb output current r ladjb = 30k 10 17 25 a v on ldo v fbp fbp regulation voltage i drvp = 0.2ma , t a = +25c 1.176 1.2 1.224 v i drvp = 0.2ma 1.174 1.2 1.226 v v f_fbp fbp fault trip point v fbp falling 0.82 0.87 0.92 v i fbp fbp input bias current v fbp = 1.35v 150 na r loadp v on load regulation i(v on ) = 0ma to 20ma 0.5 0.75 % i drvp drvp sink current max v fbp = 1.1v, v drvp = 25v 2 4 ma i l_drvp drvp leakage current v fbp = 1.5v, v drvp = 35v 0.3 2 a v off ldo v fbn fbn regulation voltage i drvn = 0.2ma , t a = +25c 0.186 0.213 0.24 v i drvn = 0.2ma 0.183 0.213 0.243 v v f_fbn fbn fault trip point v fbn rising 0.45 0.5 0.55 v i fbn fbninput bias current v fbn = 0.2v 40 na r loadn v off load regulation i(v off ) = 0ma to 20ma 0.4 0.85 % i drvn drvn source current max v fbn = 0.3v, v drvn = -6v 2 4 ma i l_drvn drvn leakage current v fbn = 0v, v drvn = -20v 0.4 5 a v logic v fbl fbl regulation voltage t a = 25c 1.178 1.2 1.222 v 1.176 1.2 1.224 v d min minimum duty cycle 20 % d max maximum duty cycle 85 % eff l logic buck efficiency 90 % ifbl fbl input bias current 20 na i linel v logic line regulation c int = 2.2nf, v in = 5v to 12v 0.03 0.25 %/v i loadl v logic load regulation c int = 2.2nf, i logic = 100ma to 450ma 0.1 0.5 % r onl gate drive on resistance pull-up 3.6 pull-down 1.9 i peakl peak drive current source 600 ma sink 900 ma i isadjl i sadjb output current r sadjb = 30k 15 a i iladjl i ladjb output current r ladjb = 30k 17 a v on -slice circuit i leak ctl ctl input leakage current ctl = a gnd or v in -1 1 a t d rise ctl to out rising prop delay 1k from drn to 8v, v ctl = 0v to 3v step, no load on out, measured from v ctl = 1.5v to out = 20% 100 ns electrical specifications v in = 5v, a vdd = 15v, v on = 20v, v off = -9v, v logic = 3v, over temperature from -40c to +85c parameter description condition min typ max unit isl97522
4 fn7445.0 december 13, 2006 t d fall ctl to out falling prop delay 1k from drn to 8v, v ctl = 3v to 0v step, no load on out, measured from v ctl = 1.5v to out = 80% 100 ns v src src input voltage range 30 v isrc src input current start-up sequence not completed 0.2 1.25 ma start-up sequence completed 150 250 a r on src src on resistance start-up sequence completed 5 14 r on drn drn on resistance start-up sequence completed 30 60 r on com com to gnd on resistance start-up sequence not completed 400 1000 1800 sequencing t on turn on delay c dly = 0.22f 30 ms t ss soft-start time c dly = 0.22f 2 ms t del1 delay between a vdd and v off c dly = 0.22f 10 ms t del2 delay between v on and v off c dly = 0.22f 17 ms t del3 delay between v off and delayed v boost c dly = 0.22f 10 ms i delb _ on delb pull-down current or resistance when enabled by the start-up sequence v delb > 0.9v 35 50 65 a v delb < 0.9v 1.2 1.6 2 k i delb_off delb pull-down current or resistance when disabled vdelb < 20v 500 na fault detection t fault fault time out c dly = 0.22f 50 ms ot over-temperature threshold 140 c logic v hi logic high threshold 2.2 v v lo logic low threshold 0.8 v i low logic low bias current 0.1 a i high logic high bias current 16 23 30 a electrical specifications v in = 5v, a vdd = 15v, v on = 20v, v off = -9v, v logic = 3v, over temperature from -40c to +85c parameter description condition min typ max unit isl97522
5 fn7445.0 december 13, 2006 typical performance curves figure 1. boost avdd efficiency figure 2. boost avdd load regulation figure 3. boost avdd line regulation figure 4. buck v logic efficiency figure 5. buck v logic load regulation figure 6. v on load regulation 0 10 20 30 40 50 60 70 80 90 100 0 500 1000 1500 2000 2500 i avdd (ma) efficiency (%) v in = 5v, a vdd = 12v v in = 12v, a vdd = 17v -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0 500 1000 1500 2000 2500 i avdd (ma) load regulation (%) v in = 12v, a vdd = 17v v in = 5v, a vdd = 12v 16.88 16.9 16.92 16.94 16.96 16.98 17 17.02 17.04 0246810121416 v in (v) a vdd (v) v o = 17v 0 10 20 30 40 50 60 70 80 90 100 0 500 1000 1500 2000 2500 i logic (ma) efficiency (%) v in = 5v, v logic = 3v v in = 12v, v logic = 3v -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0 500 1000 1500 2000 2500 i logic (ma) load regulation (%) v in = 5v, v logic = 3v v in = 12v, v logic = 3v 19.66 19.67 19.68 19.69 19.7 19.71 19.72 19.73 19.74 19.75 0 5 10 15 20 25 i von (ma) v on (v) v on = 20v isl97522
6 fn7445.0 december 13, 2006 figure 7. v off load regulation figure 8. 4ms/div v on slice circuit operation figure 9. start-up sequence figure 10. start-up sequence figure 11. in rush current figure 12. in rush current typical performance curves (continued) -8.905 -8.900 -8.895 -8.890 -8.885 -8.880 -8.875 0 5 10 15 20 25 i voff (ma) v off (v) v off = -9v ch1 = com (10v/div) ch2 = ctl (2v/div) cdly en a vdd v logic cdly v on a vdd v off a vdd (boost) i in v logic (boost mode) i in isl97522
7 fn7445.0 december 13, 2006 figure 13. in rush current figure 14. in rush current typical performance curves (continued) a vdd (buck) i in v logic (buck mode) i in isl97522
8 fn7445.0 december 13, 2006 pin descriptions pin # pin name pin description 1 drvn negative ldo base drive; open drai n of an internal p-channel mosfet. 2 delb active low control output for opt ional delay contro l for external a vdd p-channel fet; when fault is detected, this pin goes to high. 3 fbw negative ldo voltage feedback input pin; regulates to 0.2v nominal. 4 vcc1 supply input, connect to v in . 5fbba vdd regulator voltage feedback input pin; regulates to 1.2v nominal. 6 isadjb current feedback adjust for a vdd . 7 iladjb with a resistor connected from this pin to gnd se ts the current limit of the external n-channel fet for a vdd. 8cintba vdd integrator output, connect 2.2nf to analog gnd. 9 drvb gate driver output for the external n-channel switch. 10 pgndb power gnd for a vdd . 11 vhib internal drive of boost controller, connect to vdcp. 12 nc 13 isinb sense the drain voltage of the external n-channel fe t and connected to the internal current limit comparator. 14 vin main supply input. 15 en enable pin; high enable, low disabled. 16 vhil v logic boost strap mode. 17 lx v logic switch connection. 18 drvl gate driver output for external n-channel switch. 19 pgndp power gnd. 20 fbl v logic regulator voltage feedback pin; regulates to 1.2v nominal. 21 iladjl with resistor connected from this pin to gnd sets the current li mit of the external n-channel fet. 22 cintl v logic integrator output, connect 2.2nf to analog gnd. 23 isadjl current feedback adjust for v logic . 24 vdc positive supply for all internal analog circuits. 25 vdcp positive supply for exte rnal n-channel fet gate drives. 26 nc 27 drvp positive ldo base drive; open drain of an internal n-channel mosfet. 28 nc 29 acgnd low noise signal ground. 30 vref bandgap voltage bypass terminal; bypass with a 0.1 f to analog gnd; can be used as charge pump reference. 31 fbp positive ldo voltage feedback input pin; regulates to 1.2v nominal. 32 cc2 supply input, connect to v in . 33 cdly with a capacitor connect from this pin to gnd, sets the delay time for start-up se quence and fault detection timeout. 34 ctl input control for switch output. 35 enl enable pin for v logic high enable; low disabled. 36 drn lower reference voltage for switch output. 37 com switch output; when ctl = 1, com is connected to src through a 15 resistor, when ct: = 0, com is connected to drn through a 30 resistor. 38 src upper reference voltage for switch output. isl97522
9 fn7445.0 december 13, 2006 typical application diagram internal supply boost controller v on ldo v off ldo buck controller fault protection power on sequencing clock/ timing v on slice v in i sadjb v dcp delb cdly vccl enl ctl src com drn pgndp v in v sw fbl drvl v ref fbn drvn fbb drvb isinb v in v logic v off a vdd q3 v on to gate driver pgndb cintb en v n v p v dc acgnd drvp fbp vhib vhil cintl isadjl lx i ladjb vcc2 iladjl v dcp v n v p c25 0.1f l1 6.8h c11 0.1f d11 d1 v boost 15v 10fx2 c1 c30 4.7nf r20 30k r19 30k r10 10k c23 4.7f c24 4.7f c7 220nf r29 10k control input r28 10k r15 30k r16 30k c27 4.7nf r17 2k q1 r2 140k c2 i on fx3 c16 0.01f 1m r9 r8 300k vsw r1 12k q21 r3 3k r22 104k c20 4.7f -8v r21 20k c25 1f r4 3k q11 r12 237k c15 1f 25v r23 1k r11 12k r22 68k r21 l2 6.8f d2 c3 10fx4f r12 210k r13 118k q2 c32 100nf c28 0.47 d21 c24 0.1f c9 0.01f isl97522
10 fn7445.0 december 13, 2006 applications information the isl97522 provides a multiple output power supply solution for tft-lcd applications. the system consists of a high efficiency boost controller, two low cost linear-regulator controllers (v on and v off ) and a buck reglator (v logic ). table 1 below lists the recommended components. a vdd converter the main boost converter is a current mode pwm controller operating at a fixed freq uency. the 1mhz switching frequency enables the use of low profile inductor and multilayer ceramic capacitors, which results in a compact, low-cost power system for lcd panel design. the a vdd converter can operate in continuous or discontinuous inductor curr ent mode. the isl97522 is designed for continuous current mode, but it can also operate in discontinuous current mode at light load. in continuous current mode, current flows continuously in the inductor during the entire sw itching cycle in steady state operation. the voltage conversi on ratio in continuous current mode is given by (in boost mode): where d is the duty cycle of switching mosfet. figure 15 shows the function diagram of the boost controller. it uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. a comparator l ooks at the peak inductor current cycle by cycle and term inates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficienc y. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 200k is recommended. the boost converter output voltage is determined by the following equation: table 1. recommended components designation description c1, c2, c3 10f, 16v, x7r ceramic capacitor (1206) tdk c3216x7r1c106m c20 4.7f, 16v x5r ceramic capacitor (1206) tdk c3216x5r1a475k c15 1f, 25v x7r ceramic capacitor (1206) tdk c3216x7r1e105k d1 1a 20v low leakage schottky rectifier (case 457-04) on semi mbrm120et3 d11, d12, d21 200ma 30v schottky barrier diode (sot-23) fairchild bat54s l1 6.8mh 4.6a inductor coilcraft do3316p-682ml q1,q2 6.3a 30v single n-channel logic level powertrench mosfet (sot-23) fairchild fdc655an q3 -2a -30v single p-channel logic level powertrench mosfet (supersot-3) fairchild fdn360p q11 200ma 40v pnp amplifier (sot-23) fairchild mmbt3906 q21 200ma 40v npn amplifier (sot-23) fairchild mmbt3904 a vdd v in --------------- - 1 1d ? ------------- = (eq. 1) a vdd r 1 r 2 + r 1 -------------------- - v fbb = (eq. 2) isl97522
11 fn7445.0 december 13, 2006 the internal current limit circui try is shown in figure 16. the circuit senses the voltage across the r ds(on) when the mosfet is on; then compare it to the internal voltage reference to realize the current limit. the internal voltage reference is generated by a 10ma current and any additional current set at i ladjb pin flowing through an 8k resistor. the voltage reference is based on the following equation: where v iladjb is the voltage at pin i ladj . where v isad is the voltage at pin i sad . where v be 0.7v the external resistor r 1 should be chosen in the order of 100k to generate a of current. hence the maximum output current is determined by the following equation: where i l is the peak to peak inductor ripple current, and is set by: pwm logic controller buffer current limit ref generator oscillator slope compensation osc reference generator v ref shutdown & startup control v in v boost drvb i sin i ladj gm amplifier uvlo comparator current amplifier current limit comparator i sadj figure 15. function diagram of the boost controller fbb cintb v threshold v iladjb r 1 ----------------------- - 10 a + ?? ?? ?? 8k = (eq. 3) v isad v ref v be ? 1k i sad ? = i sad v isad r1 ----------------- = (eq. 4) - + logic controller lx i ladjb r 1 v ref 1k 8k drvb i sinb v dd 10a figure 16. current limit block diagram i omax v threshold r dson --------------------------------------- ? ? ? i l 2 -------- ? ? v in v o --------- ? = (eq. 5) i l v in l --------- d f s ---- - = (eq. 6) isl97522
12 fn7445.0 december 13, 2006 f s is the switching frequ ency; d is the duty cycle. to overcome the variation in external lx driver r ds(on) , an input is provided (iladj) to accommodate 5 different bands of r ds(on) by using 5 different select ion resistors. internally, the iladj resistor adjusts two things: 1.the current limit; 2.the current feedback being used. this keeps the dc-dc loop stable and the current limit the same over a wide range of external drive fets. alternatively, the current limit can be changed for the same fet by varying the resistor. this would affect the stability of the system somewhat (because the current feedback changes) but be selected appr opriately to accommodated the change. the integrator loop should keep the load regulation within limits as long as it doesn't run out of dynamic adjustment range when current feedback gets larger than intended. this could be determined by measuring how close to the upper clamp limit the voltage on the cint pin voltage gets under maximum load current. here are the resistor settings on iladj which select the five r ds(on) ranges: 1/ 0ohms (cfb factor 1, "cfb" are the relative current feedback factors) 2/ 30k (cfb factor 1/1.8) 3/ 83k (cfb factor 1/3.3) 4/ 182k (cfb factor 1/5.7) 5/ >370k (cfb factor 1/10) 1/ sets maximum internal current feedback and minimum ilimit, used for low ron fets. 5/ sets minimum internal current feedback and maximum ilimit, used for large ron fets. the current limit factors shoul d be the inverse of the cfb values. input capacitor the input capacitor is used to supply the current to the converter. it is recommended that c in be larger than 10f. the reflected ripple voltage will be smaller with larger c in . the voltage rating of input capacitor should be larger than maximum input voltage. boost inductor a 6.8h inductor is recommended. the inductor must be able to handle the following average and peak current: boost mosfet due to the parasitic inductanc e of the trace, the mosfet will experience spikes higher t hat the output voltage when the mosfet turns off. thus, a mosfet with enough voltage margin is needed. the r ds(on) of the mosfet is critical for power dissipation and current limit. a mosfet with low r ds(on) is desired to get high efficiency and output current, but very low r ds(on) will reduce the loop stability. a mosfet with 20m to 50m r ds(on) is recommended. some recommended mosfets are shown in table 2. rectifier diode a high-speed diode is desired due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and lo w forward voltage. the rectifier diode must meet the output current and peak inductor current requirements. output capacitor the output capacitor supplies the load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the esr of output capacitor, and the charging and discharging of the output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capacitor should be greater than the maximum output voltage. d v o v in ? v o ----------------------- - = (eq. 7) table 2. recommended mosfets part number manufacturer feature fdc655an fairchild semiconductor 6.3a, 30v, r ds(on) = 23m fds4488 fairchild semiconductor 7.9a, 30v, r ds(on) = 22m si7844dp vishay 10a, 30v, r ds(on) = 22m si6928dq vishay 20a, 30v, r ds(on) = 30m i lavg i o 1d ? ------------- = (eq. 8) i lpk i lavg i l 2 -------- + = (eq. 9) v ripple i lpk esr v o v in ? v o ----------------------- - i o c out --------------- - 1 f s ---- - + = (eq. 10) isl97522
13 fn7445.0 december 13, 2006 pi mode c int (c 23 ) and r int (r 10 ) the ic is designed to operate with a minimum c 23 capacitor of 4.7nf and a minimum c 2 (effective) = 10f. note that, for high voltage a vdd , the voltage coefficient of ceramic capacitors (c 2 ) reduces their effective capacitance greatly; a 16v 10f ceramic can drop to around 3f at 15v. to improve the transient load response of a vdd in pi mode, a resistor may be added in series with the c 23 capacitor. the larger the resistor the lower the overshoot but at the expense of stability of the converter lo op - especially at high currents. with l = 10h, a vdd = 15v, c 23 = 4.7nf, c 2 (effective) should have a capacitance of greater than 10f. r int (r 7 ) can have values up to 5k for c 2 (effective) up to 20f and up to 10k for c 2 (effective) up to 30f. larger values of r int (r 7 ) may be possible if maximum a vdd load currents less than the current limit are used. to ensure a vdd stability, the ic should be operated at the maximum desired current and then the transient load response of a vdd should be used to determine the maximum value of r int operation of the delb output function an open drain delb output is provided to allow the boost output voltage, developed at c 2 (see application diagram), to be delayed via an external switch (q3) to a time after the v boost supply and negative v off charge pump supply have achieved regulation during the start-up sequence shown in figure 21. this then allows the a vdd and v on supplies to start-up from 0v instead of the normal offset voltage of v in -v diode (d 1 ) if q3 were not present. when delb is activated by the start-up sequencer, it sinks 50a allowing a controlled turn- on of q3 and charge-up of c 9 . c 16 can be used to control th e turn-on time of q3 to reduce inrush current into c 9 . the potential divider formed by r 9 and r 8 can be used to limit the v gs voltage of q3 if required by the voltage rating of this device. when the voltage at delb falls to less than 0.6v, the sink current is increased to ~1.2ma to firmly pull delb to 0v. the voltage at delb is monitored by the fault protection circuit so that if the initial 50a sink current fails to pull delb below ~0.6v after the start-up sequencing has completed, then a fault condition will be det ected and a fault time-out ramp will be initiated on the c del capacitor (c 7 ). linear-regulator controllers (v on , v off ) the isl97522 includes two independent linear-regulator controllers, in which one is a positive output voltage (v on ), and one is negative. the v on and v off linear-regulator controller function diagrams are shown in figures 17, and 18, respectively. calculation of the linear regulator base-emitter resistors ( r bp and r bn ) for the pass transistor of the linear regulator, low frequency gain (hfe) and unity gain freq. (f t ) are usually specified in the datasheet. the pass transistor adds a pole to the loop transfer function at f p = f t /hfe. therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency low gain switching transistor. further improvement can be obtained by adding a base-emitter resistor r be (r bp , r bl , r bn in the functional block diagram), which increase the pole frequency to: f p =f t *(1+ hfe *re/r be )/hfe, where re = kt/qic. so choose the lowest value r be in the design as long as there is still enough base current (i b ) to support the maximum output current (i c ). we will take as an example the v on linear regulator. if a fairchild mmbt3906 pnp transistor is used as the external pass transistor, q11 in the application diagram, then for a maximum v on operating requirement of 50ma the data sheet indicates hfe_min = 30. the base-emitter saturation voltage is: vbe_max = 0.7v. for the isl97522, the minimum drive current is: i_drvp_min = 2ma. the minimum base-emitter resistor, r bp , can now be calculated as: r bp _min = v be _max/(i_drvp_min - ic/hfe_min) = 0.7v/(2ma - 50ma/30) = 2.1k this is the minimum value that can be used - so, we now choose a convenient value greater than this minimum value; say 3k . larger values may be used to reduce quiescent current, however, regulation may be adversely affected, by supply noise if r bp is made too high in value. - + - + 36v esd clamp gmp ldo_on pg_ldop 1 : np fbp drvp 3k r bp a vdd 0.1f 0.1f cp (to 36v) r p2 r p1 c on v on (to 35v) isinb 0.9v figure 17. v on function block diagram isl97522
14 fn7445.0 december 13, 2006 the v on power supply is used to power the positive supply of the row driver in the lcd pa nel. the dc/dc consists of an external diode-capacitor c harge pump powered from the switch node (lxb) of the a vdd converter, followed by a low dropout linear regulator (ldo_on). the ldo_on regulator uses an external pnp transistor as the pass element. the onboard ldo controller is a wide band (>10mhz) transconductance amplifier ca pable of 5ma output current, which is sufficient for up to 50ma or more output current under the low dropout condition (forced beta of 10). typical v on voltage supported by the isl97522 ranges from +15v to +36v. a fault comparator is also included for monitoring the output voltage. the undervoltage threshold is set at 16.7% below the 1.2v reference. the v off power supply is used to power the negative supply of the row driver in the lcd panel. the dc/dc consists of an external diode-capacitor charge pump powered from the switch node (lxb) of the a vdd converter, followed by a low dropout linear regulator (ldo_off). the ldo_off regulator uses an external npn transistor as the pass element. the onboard ldo controller is a wide band (>10mhz) transconductance amplifier capable of 5ma output current, which is sufficient for up to 50ma or more output current under the low dr opout condition (forced beta of 10). typical v off voltage supported by the isl97522 ranges from -5v to -25v. a fault comparator is also included for monitoring the output voltage. the undervoltage threshold is set at 20% above the 1.0v reference level.set- up ldos output voltage. set-up ldos output voltage refer to typical application diagram, the output voltages of v on , v off , and v logic are determined by equations 11 and 12: charge pump to generate an output voltage higher than a vdd , single or multi stages of charge pumps are needed. the number of stage is determined by the input and output voltage. for positive charge pump stages: where v ce is the dropout voltage of the pass component of the linear regulator. it ranges from 0.3v to 1v depending on the transistor. v f is the forward-voltage of the charge pump rectifier diode. the number of negative charge pump stages is given by: to achieve high efficiency and low material cost, the lowest number of charge pump stages , which can meet the above requirements, is always preferred. charge pump output capacitors a ceramic capacitor with low esr is recommended. with ceramic capacitors, the output ripple voltage is dominated by the capacitance value. the capacitance value can be chosen by equation 15. where f soc is the switching frequency. high charge pump output voltage (>36v) applications in the applications where the charge pump output voltage is over 36v, an external npn transistor need to be inserted into between drvp pin and base of pass transistor q3 as shown in figure 19; or the linear regulator can control only one stage charge pump and regulate the final charge pump output as shown in figure 20. - + - + 36v esd clamp gmn ldo_off 1 : nn fbn drvn 0.1f 0.1f cp (to -26v) r bn c off v off (to -20v) 3k isinb r n1 r n2 v ref pg_ldon 0.4v figure 18. v off function block diagram v on v fbp 1 r 12 r 11 --------- - + ?? ?? ?? = (eq. 11) v off v fbn r 22 r 21 --------- - v fbn v ref ? () + = (eq. 12) n positive v out v ce v input ? + v input 2v f ? ------------------------------------------------------------- - (eq. 13) n negative v output v ce + v input 2v f ? ------------------------------------------------ - (eq. 14) c out i out 2v ripple f osc ------------------------------------------------------ (eq. 15) isl97522
15 fn7445.0 december 13, 2006 discontinuous/continuous boost operation and its effect on the charge pumps the isl97522 v on and v off architecture uses lx switching edges to drive diode charge pumps from which ldo regulators generate the v on and v off supplies. it can be appreciated that should a regular supply of lx switching edges be interrupted, for example during discontinuous operation at light a vdd boost load currents, then this may affect the performance of v on and v off regulation - depending on their exact loading conditions at the time. to optimize v on /v off regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted, by suitable choice of inductor given v in , v out , switching frequency and the a vdd current loading, to be in continuous operation. the following equation gives the boundary between discontinuous and continuous boos t operation. for continuous operation (lx switching every clock cycle) we require that: i(a vdd _load) > d*(1-d)*v in /(2*l*f osc ) where the duty cycle, d = (a vdd - v in )/a vdd for example, with v in = 5v, f osc = 1.0mhz and a vdd = 12v we find continuous operat ion of the boost converter can be guaranteed for: l = 10h and i(a vdd ) > 61ma l = 6.8h and i(a vdd ) > 89ma l = 3.3h and i(a vdd ) > 184ma buck converter the buck converter is the step down converter, which supplies the current to the logic circuit of the lcd system. in the continuous current mode, the relationship between input voltage and output voltage is as following: where d is the duty cycle of the switching mosfet. because d is always less than 1, the output voltage of buck converter is lower than input voltage. t he feedback resistors the buck converter output voltage is determined by the following equation: where r12 and r13 are the feedback resistors of buck converter to set the output vo ltage current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 300 is recommended. buck converter input capacitor the capacitor should support the maximum ac rms current which happens when d = 0.5 and maximum output current. where i o is the output current of the buck converter. v in or a vdd charge pump output 3k q3 fbp isl97522 drvp npn cascode transistor v on figure 19. cascode npn transistor configuration for high charge pump output voltage (>36v) v on (>36v) 0.1f 0.1f 0.1f 0.1f 3k 0.47f 0.22f 0.1f a vdd lx q3 fbp isl97522 drvp figure 20. the linear regulator controls one stage of charge pump v logic v in -- ----------------- - d = (eq. 1 6 v logic r 12 r 13 + r 13 -------------------------- - v fbl = (eq. 17) i acrms c in () d1d ? () ? i o ? = (eq. 18) isl97522
16 fn7445.0 december 13, 2006 buck inductor an inductor value in the rang e 3.3-10h is recommended for the buck converter. besides the inductance, the dc resistance and the saturation current should also be considered when choosing buck inductor. low dc resistance can help maintain high efficiency, and the saturation current ra ting should be at least maximum output current plus half of ripple current. buck mosfet the principle to select buck mo sfet is similar to that of boost. the voltage of stress of buck converter should be maximum input voltage plus reasonable margin, and the current rating should be over the maximum output current. the r ds(on) of this mosfet should be in the range from 20m to 50m . rectifier diode (buck converter) a schottky diode is recommended due to fast recovery and low forward voltage. the reverse voltage rating should be higher than the maximum input voltage. the average current should be as the following equation, where i o is the output current of buck converter. output capacitor (buck converter) four 10f or two 22f ceramic capacitors are recommended for this part. the overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer. pi loop compensation (buck converter) the buck converter of isl97522 can be compensated by a rc network connected from ci ntl pin to ground. c27 = 4.7nf and r17= 2k rc network is used in the demo board. the larger value resistor can lower the transient overshoot, however, at the expense of stability of the loop. the stability can be optimized in a similar manner to that described in the section on "pi loop compensation (boost converter)?. bootstrap capacitor (c28) this capacitor is used to provid e the supply to the high driver circuitry for the buck mosfet . the bootstrap supply is formed by an internal diode and capacitor combination. a 1f is recommended for isl97522. a low value capacitor can lead to overcharging and in turn damage the part. if the load is too light, the on-time of the low side diode may be insufficient to replenish the bootstrap capacitor voltage. in this case, if v in -v buck < 1.5v, the internal mosfet pull-up device may be unable to turn-on until v logic falls. hence, there is a minimum load requirement in this case. the minimum load can be adjusted by the feedback resistors to fbl. the bootstrap capacitor can only be charged when the higher side mosfet is off. if the load is too light which can not make the on time of the low side diode be sufficient to replenish the boot strap capacitor, the mosfet can?t turn on. hence there is minimum load requirement to charge the bootstrap capacitor properly. start-up sequence figure 21 shows a detailed start-up sequence waveform. for a successful power-up, there should be six peaks at v cdly . when a fault is detected, the device will latch off until either en is toggled or the input supply is recycled. if en is l, the device is powered down. if en is h, and the input voltage (v in ) exceeds 2.5v, an inte rnal current source starts to charge c dly to an upper threshold using a fast ramp followed by a slow ramp. if en is low at this point, the c dly ramp will be delayed until en goes high. the first four ramps on c dly (two up, two down) are used to initialize the fault protection switch and to check whether there is a fault condition on c dly or v ref . if a fault is detected, the outputs and the in put protection will turn off and the chip will power down. if no fault is found, c cdly continues ramping up and down until the sequence is completed. during the second ramp, the device checks the status of v ref and over temperature. initially the boost is not enabled so v boost rises to v in - v diode through the output diode. hence, there is a step at v boost during this part of the start-up sequence. if this step is not desirable, an external pmos fet can be used to delay the output until the boost is ena bled internally. the delayed output appears at a vdd . v boost soft-starts at the beginning of the third ramp. the soft-start ramp depends on the value of the c dly capacitor. for c dly of 220nf, the soft-start time is ~2ms. v off turns on at the start of the fourth peak. at the fifth peak, the open drain o/p delb goes low to turn on the external pmos q3 to generate a delayed v boost output. v on is enabled at the beginning of the sixth ramp. a vdd , v off , delb and v on are checked at end of this ramp. vlogic?s start-up is controlled by enl. when enl is l, vlogic is off, and when enl is h, v logic is on. i avg 1d ? () *i o = (eq. 19) isl97522
17 fn7445.0 december 13, 2006 v cdly en v ref v boost v off delayed v boost v on v ref on a vdd , soft-start v off on delb on v on soft-start fault detected chip disabled normal operation fault present start-up sequence timed by c dly t del1 t os t on t del2 figure 21. isl97522 start-up sequence enl v on slice v logic isl97522
18 fn7445.0 december 13, 2006 fault protection during the startup sequence, prior to boost soft-start, v ref is checked to be within 20% of its final value and the device temperature is checked. if either of these are not within the expected range, the part is disabled until the power is recycled or en is toggled. if c delay is shorted low, then the sequence will not start, while if c delay is shorted h, the first down ramp will not occur and the sequence will not complete. once the start-up sequence is completed, the chip continuously monitors c dly , delb, fbp, fbl, fbn, v ref and fbb for faults. during this time, the voltage on the c dly capacitor remains at 1.15v until either a fault is detected, or the en pin is pulled low. a fault on c delay , v ref or temperature will shut down the chip immediately. if a fault on any other output is detected, c delay will ramp up linearly with a 5a (typical) current to the upper fault threshold (typically 2.4v), at which point the chip is disabled until the power is recycled or en is toggled. if the fault condition is removed prior to the end of the ramp, the voltage on the c dly capacitor returns to 1.15v. typical fault thresholds for fbp, fbl, fbn and fbb are included in the tables. delb fault threshold is typically 0.6v. c intb and c intl have an internal current-limited clamp to keep the voltage within their normal ranges. if they are shorted low, the regulators wi ll attempt to regulate to 0v. if any of the regulated outputs (avdd, v on , v off or v logic ) are driven above their target levels the drive circuitry will switch off until the output returns to its expected value. if avdd and v logic are excessively loaded, the current limit will prevent damage to the chip. while in current limit, the part acts like a current s ource and the regulated output will drop. if the output drops below the fault threshold, a ramp will be initiated on c delay and, provided that the fault is sustained, the chip will be disabled on completion of the ramp. in some circumstances, (depending on ambient temperature and thermal design of the boa rd), continuous operation at current limit may result in the over-temperature threshold being exceeded, which will c ause the part to disable immediately. all i/o also have esd protection, which in many cases will also provide overvoltage protecti on, relative to either ground or v dd . however, these will not generally operate unless abs max ratings are exceeded. component selection for start-up sequencing and fault protection the c ref capacitor is typically set at 220nf and is required to stabilize the v ref output. the range of c ref is from 22nf to 1f and should not be more than five times the capacitor on c del to ensure correct start-up operation. the c del capacitor is typically 220nf and has a usable range from 47nf minimum to several microfarads - only limited by the leakage in the capacitor reaching a levels. c del should be at least 1/5 of the value of c ref (see above). note with 220nf on c del the fault time-out will be typically 50ms and the use of a larger/smaller value will vary this time proportionally (e.g. 1f will give a fault time-out period of typically 230ms). fault sequencing the isl97522 has an advanc ed fault detection system which protects the ic from bo th adjacent pin shorts during operation and shorts on the output supplies. a high quality layout/design of the pcb, in respect of grounding quality and decoupling is necessary to avoid falsely triggering the fault detection scheme - especially during start-up. the user is di rected to the layout guidelines and component selection sections to avoid problems during initial evaluation and prototype pcb generation. over-temperature protection an internal temperature sens or continuously monitors the die temperature. in the event that the die temperature exceeds the thermal trip point of 140c, the device will shut down. layout recommendation the device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the pcb layout. pcb layout is critical, especially at high switching frequency. there are some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors , boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v ref , v dc and v dcp bypass capacitors close to the pins. 3. minimize the length of trac es carrying fast signals and high current. 4. all feedback networks shoul d sense the output voltage directly from the point of load, and be as far away from lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connected at only one point near the main decoupling capacitors. isl97522
19 fn7445.0 december 13, 2006 6. the exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the pcb. this contact area should have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available, to maximize thermal dissipation away from the ic. 7. to minimize the thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. a signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (r 1 , r 11 , r 41 ) and the v ref capacitor, c 25 , the c delay capacitor c 7 and the integrator capacitor c 30 , c 27 . 9. minimize feedback input track lengths to avoid switching noise pick-up. isl97522
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7445.0 december 13, 2006 isl97522 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) pin #1 i.d. mark 2 1 3 (n-2) (n-1) n (n/2) 2x 0.075 top view (n/2) ne 2 3 1 pin #1 i.d. (n-2) (n-1) n b l n leads bottom view detail x plane seating n leads c see detail "x" a1 (l) n leads & exposed pad 0.10 side view 0.10 b a m c c b a e 2x 0.075 c d 3 5 7 (e2) (d2) e 0.08 c c (c) a 2 c l38.5x7b (one of 10 packages in mdp0046) 38 lead quad flat no-lead plastic package (compliant to jedec mo-220) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 0.00 0.02 0.05 - d 5.00 bsc - d2 3.50 ref - e 7.00 bsc - e2 5.50 ref - l 0.35 0.40 0.45 - b 0.23 0.25 0.27 - c 0.20 ref - e 0.50 bsc - n 38 ref 4 nd 7 ref 6 ne 12 ref 5 rev 0 5/06 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminals on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be s quare or circular in shape with radius (b/2) as shown.

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